FIGS. 6-9 show a conventional boosted potential generating circuit. In FIG. 6, the boosted potential generating circuit has a clock input node 1 for receiving a clock (CLK) signal of binary levels consisting of a ground potential (0V) and a power supply potential (Vcc), as shown in FIG. 8(a), and a boosted potential node 2 for supplying a boosted potential. A load capacitor 3 is driven by the boosted potential supplied to the boosted potential node 2, and the load capacitor 3 is a parasitic capacitance existing between the boosted potential node and the ground potential node. An N-channel type MOS transistor 4 serves as a drive transistor for the boosted potential generating circuit, and is connected between the boosted potential node 2 and a first node 5. A gate electrode is connected to a second node 6, and a back gate (a p-well region 12 in FIG. 7) is connected to an output node of potential generating means (not shown) for outputting a negative potential Vbb.
A first buffer means 7 receives the clock signal from the clock input node 1 and outputs a first signal in phase with the clock signal. The first buffer means 7 comprises an even number of stages, or in this example, inverters 7a and 7b of two stages. A first capacitive element 8 has a pair of electrodes, where one electrode receives the first signal from the first buffer means 7 and the other electrode is connected to the first node 5. A second buffer means 9 receives the clock signal from the clock input node 1 and outputs a second signal in phase with the clock signal. The second buffer means 9 comprises an even number of stages, or in this example, inverts 9a and 9b of two stages. A second capacitor 10 has a pair of electrodes, where one electrode receives the second signal from the second buffer means 9 and the other electrode is connected to the second node 6.
FIG. 7 illustrates the boosted potential generating circuit incorporated in a semiconductor memory device, such as a dynamic random access memory (DRAM), with the N-channel type MOS transistor 4 having a pair of source and drain regions 13 and 14 formed in a p-well region 12 formed on a major surface of a semiconductor substrate 11, and a gate electrode 15. Since the semiconductor substrate 11 is supplied with the negative potential Vbb, the negative potential Vbb is also supplied back gate of the N-channel type MOS transistor 4. In FIG. 7, a P-channel type MOS transistor is also fabricated with the N-channel type MOS transistor 4. The P-channel type MOS transistor comprises a pair of source and drain regions 17 and 18 formed in an n-well region 16 formed on the major surface of a semiconductor substrate 11, and a gate electrode 19. Such a structure is generally referred to as a twin well structure. An oxide film 20 surrounds an element forming region to electrically isolate the elements.
The first and second nodes 5 and 6 in FIG. 6 are precharged to the power supply potential Vcc (or a potential lower than the power supply potential by a threshold voltage of a MOS transistor) prior to application of the boosted potential to the boosted potential node 2 by a precharge means (not shown). Before the boosted potential is supplied to the boosted potential node 2 (or before time T0 shown in FIG. 8), the first and second nodes 5 and 6 are precharged to the power supply potential Vcc by the precharge means. As a result, the potential of the boosted potential node 2 is set at Vcc-Vth4 by conduction of the N-channel type MOS transistor 4, where Vth4 is a threshold voltage of the N-channel type MOS transistor. Referring to a waveform diagram shown in FIG. 8, the operation of the boosted potential generating circuit is as follows.
At time T0, i.e., when the clock signal shown in FIG. 8(a) is fed to the clock input node 1, inputs potentials of the first and second buffer means 7 and 9 rise to the power supply potential, and output potentials of the first and second buffer means 7 and 9 rise from the ground potential (0V) to the power supply potential Vcc, thereby raising the potentials of the first and second capacitive elements 8 and 10. The electrodes on one side of the first and second capacitive elements 8 and 10 are boosted from the ground potential (0V) to the power supply potential Vcc, so that the potentials of the first and second nodes 5 and 6 are raised from Vcc, which is the precharge potential, to two times Vcc by capacitive coupling of the first and second capacitive elements 8 and 10.
The N-channel type MOS transistor 4 then conducts since its drain potential becomes 2Vcc; its gate potential becomes 2Vcc; and its source potential becomes Vcc-Vth4. Further, the charges at the first capacitive element 8 flow into the boosted potential node 2 through the N-channel type MOS transistor 4 and are stored thereat, so that the potential of the boosted potential node 2 is boosted to Vcc-Vth4+.alpha.. The boosted portion .alpha. of the potential at the boosted potential node 2 is determined from the capacitance shared between the capacitances of the first capacitive element 8 and the load capacitor 3.
Then, at time T1, i.e., when the clock signal falls to the ground potential, the potentials of the first and second buffer means 7 and 9 also fall to the ground potential, so that the potentials of the first and second nodes 5 and 6 fall to Vcc by the capacitive coupling of the first and second capacitive elements 8 and 10. The N-channel type MOS transistor 4 becomes nonconductive, because its drain potential equals Vcc; its gate potential equals Vcc; and its source potential equals Vcc-Vth4+.alpha.. Hence, there is no charge flow from the boosted potential node 2 to the first node 5.
Next, when the clock signal is raised again to the power supply potential Vcc at time T2, the outputs of the first and second buffer means 7 and 9 rise from the ground potential to the power supply potential Vcc, thereby (similar to above) raising the potentials of the first and second capacitive elements 8 and 10, and boosting the potentials of the first and second nodes 5 and 6 to two times Vcc. Further, the N-channel type MOS transistor 4 becomes conductive, and the charges at the first capacitive element 8 flow into the boosted potential node 2 through the N-channel type MOS transistor 4, thereby further raising the potential of the boosted potential node 2. The potential of the boosted potential node 2 is thus boosted stepwise at every rise of the clock signal from the ground potential to the power supply potential, and the boosted potential of 2Vcc-Vth4 is finally obtained at the boosted potential node 2.
As shown in FIG. 9, since the N-channel type MOS transistor 4, in which the negative potential Vbb is fed to the back gate, is used as the drive transistor, the substrate potential (potential of the p-well region 12, i.e., the effective substrate potential) viewed from the source electrode (or the electrode connected to the boosted potential node 2 in this situation) is very deep, and the threshold voltage Vth4 is large. Hence, the boosted potential Vpp obtained at the boosted potential node 2 cannot obtain a high potential.
Another type of a boosted potential generating circuit is shown in FIGS. 10-12, which is not affected from the threshold voltage Vth4, and hence is capable of rendering a higher boosted potential Vpp at the boosted potential node 2. The boosted potential generating circuit of FIG. 10 includes an N-channel type MOS transistor 4 with a structure capable of being independently fed with a potential at the back gate (p-well region) which is electrically connected to the drain electrode.
When the boosted potential generating circuit is incorporated in a semiconductor memory device, for example, such as a DRAM, as shown in FIG. 11, the N-channel type MOS transistor comprises a p-well region 12 formed in an n-well region 21 which is formed on a major surface of a semiconductor substrate 11, a pair of source and drain regions 13 and 14 formed in the p-well region 12, and a gate electrode 15. The p-well region 12 can be electrically isolated from the semiconductor substrate 11, since the p-well region 12 is surrounded by the n-well region 21, and can be fed independently with a potential. Accordingly, the circuit shown in FIG. 10 is realized by electrically connecting the p-well region 12, i.e., the back gate, with the drain electrode. Such a structure is generally referred as a triple well structure. The P-channel type MOS transistor is the same as the transistor shown in FIG. 7.
Referring to a waveform diagram shown in FIG. 12, the operation of the boosted potential generating circuit illustrated in FIG. 10 is as follows. Before the boosted potential is fed to the boosted potential node 2 (or before time T0 shown in FIG. 12), the first and second nodes 5 and 6 are precharged to the power supply potential Vcc by the precharge means (not shown). As a result, the potential of the boosted potential node 2 is set at Vcc-Vth4 by conduction of the N-channel type MOS transistor 4.
When the clock signal of FIG. 12(a) is fed to the clock input node 1 at time T0, the input potentials of the first and second buffer means 7 and 9 rise to the power supply potential. The output potentials of the first and second buffer means 7 and 9 rise from the ground potential (0V) to the power supply potential Vcc. The potentials of the first and second capacitive elements 8 and 10 are raised, and the potentials of the first and second nodes 5 and 6 rise from Vcc, the precharge potential, to two times Vcc by capacitive coupling of the first and second capacitive elements 8 and 10. The N-channel type MOS transistor 4 conducts, and the charges at the first capacitive element 8 flow to the boosted potential node 2 through the N-channel type MOS transistor 4, thereby boosting the potential of the boosted potential node 2 to Vcc-Vth4 +.alpha..
When the clock signal drops to the ground potential at time T1, the potentials of the first and second buffer means 7 and 9 drop to the ground potential, and the potentials of the first and second nodes 5 and 6 decrease to Vcc by the capacitive coupling of the first and second capacitive elements 8 and 10. At time T1, the N-channel type MOS transistor 4 becomes non-conductive, and no charges flow from the boosted potential node 2 to the first node 5.
When the clock signal is raised again to the power supply potential Vcc at time T2, the outputs of the first and second buffer means 7 and 9 are also raised from the ground potential to the power supply potential Vcc. Similarly to the above, the potentials of the first and second capacitive elements 8 and 10 are increased, and the potentials of the first and second nodes 5 and 6 are boosted up to two times Vcc. Accordingly, the N-channel type MOS transistor 4 becomes conductive, and the charges at the first capacitive element 8 flow into the boosted potential node 2 through the N-channel type MOS transistor 4, thereby further raising the potential of the boosted potential node 2.
Accordingly, the potential of the boosted potential node 2 is boosted stepwise at every rise of the clock signal from the ground potential to the power supply potential Vcc. Since the p-well region 12 and the drain of the N-channel type MOS transistor 4 are electrically connected with each other, and the potential is transmitted via the PN junction from the p-well region 12 to the source region (consisting of an n-type diffusion region), a boosted potential Vpp equal to 2Vcc-Vjv is eventually obtained at the boosted potential node 2. The voltage Vjv is a PN junction voltage between the p-well region 12 and the n+ diffusion region constituting the source, and generally, is about 0.6 volts.
The boosted potential generating circuit of FIG. 10 obtains a higher boosted potential Vpp than the boosted potential generating circuit of FIG. 6 whose boosted potential Vpp equals 2Vcc-Vth4, where Vth4&gt;Vjv. However, there is an increase in the process steps and cost to manufacture the boosted potential generating circuit of FIG. 10, since the N-channel type MOS transistor 4 formed from the triple well structure is used as the drive transistor.
Alternatively, a p-channel type MOS transistor can be used as a drive transistor, as illustrated in FIGS. 13-15. In FIG. 13, a P-channel type MOS transistor 22, serving as a drive transistor for the boosted potential generating circuit, is connected between the boosted potential node 2 and the first node 5. The gate electrode is connected Lo the second node 6. The P-channel type MOS transistor 22 comprises a transistor structure of either the P-channel type MOS transistor in the twin well structure of FIG. 7 or the P-channel type MOS transistor in the triple well structure of FIG. 11, in which the back gate (the n-well 16 region) is electrically connected to the drain electrode.
A level conversion circuit 23 receives a clock signal having a Vcc amplitude from the clock input node 1. Based on the boosted potential Vpp at the boosted potential node 2, the level conversion circuit 23 outputs to the second node 6 a second signal having a Vpp amplitude and a phase opposite to the clock signal. FIG. 14 illustrates in detail the level conversion circuit 23.
An N-channel type MOS transistor 24 has a gate electrode connected to the clock input node 1 and a source electrode connected to the ground potential. An inverter circuit 25 receiving the clock signal from the clock input node reverses the phase of the clock signal. An N-channel type MOS transistor 26 has a gate electrode which receives the clock signal whose phase is made opposite at the inverter circuit 25, and a source electrode connected to the ground potential node.
A P-channel type MOS transistor 27 includes a source electrode connected to the boosted potential node 2, a drain electrode connected to the drain electrode of the N-channel type MOS transistor 24, a gate electrode connected to the drain electrode of the N-channel type MOS transistor 26, and a back gate connected to the boosted potential node 2. A P-channel type MOS transistor 28 includes a source electrode connected to the boosted potential node 2, a drain electrode connected to the drain electrode of the N-channel type MOS transistor 26, a gate electrode connected to the drain electrode of the N-channel type MOS transistor 24, and a back gate connected to the boosted potential node 2. Further, the P-channel type MOS transistor 28 is cross-coupled with the P-channel type MOS transistor 27.
An N-channel type MOS transistor 29 has a gate electrode connected to a connection point between the drain electrode of the P-channel type MOS transistor 28 and the drain electrode of the N-channel type MOS transistor 26, a drain electrode connected to the second node 6, and a source electrode connected to the ground potential. A P-channel type MOS transistor 30 includes a gate electrode connected to the connection point between the drain electrode of the P-channel type MOS transistor 28 and the drain electrode of the N-channel type MOS transistor 26, a drain electrode connected to the second node 6, a source electrode connected to the boosted potential node 2, and a back gate connected to the boosted potential node 2. The P-channel type MOS transistor 30 constitutes an inverter circuit with the N-channel type MOS transistor 29, and delivers to the second node 6 a second signal having the Vpp amplitude and a phase opposite to the clock signal of the Vcc amplitude.
When the boosted potential generating circuit of FIG. 13 is incorporated in a semiconductor memory device, such as a DRAM, the N-channel type MOS transistors 24, 26 and 29 and the N-channel type MOS transistor of the inverter circuit 25 can be any MOS transistor structure of either the N-channel type MOS transistor in the twin well structure of FIG. 7 or the N-channel type MOS transistor in the triple well structure of FIG. 11. The P-channel type MOS transistors 27, 28 and 30 and the P-channel type MOS transistor of the inverter circuit 25 can be any MOS transistor structure of either the P-channel type MOS transistor in the twin well structure of FIG. 7 or the P-channel type MOS transistor in the triple well structure of FIG. 11.
The first and second nodes 5 and 6, and the boosted potential node 2 are precharged to the power supply potential Vcc (or a potential equal to the power supply potential minus the threshold voltage of the MOS transistor) by the precharge means (not shown) prior to supplying the boosted potential to the boosted potential node 2. Referring to a waveform diagram shown in FIG. 15, the operation of the boosted potential generating circuit of FIG. 14 is as follows. First, the first and second nodes 5 and 6 and the boosted potential node 2 are precharged to the power supply potential Vcc by the precharge mans before the boosted potential is supplied to the boosted potential node 2 (or before time T0 shown in FIG. 8).
When the clock input node 1 receives the clock signal, as shown in FIG. 15(a), and the power supply potential is applied to the input of the first buffer means 7 at time T0, the output of the first buffer means 7 is also raised from the ground potential to the power supply potential Vcc. The one electrode of the first capacitive element 8 is raised from the ground potential to the power supply potential Vcc, such that the potential of the first node 5 is boosted from Vcc to two times Vcc by capacitive coupling of the first capacitive element 8.
Meanwhile, when the input of the level conversion circuit 23 changes based on the clock signal applied at the clock input node 1 from the ground potential to the power supply potential, its output node changes from the boosted potential Vpp (or at an initial state of potential Vcc of the precharge potential) to the ground potential which is fed to the second node 6.
In the level conversion circuit 23 shown in FIG. 14, the N-channel type MOS transistor 24 and the P-channel type MOS transistor 28 become conductive, and the N-channel type MOS transistor 26, and the P-channel type MOS transistor 27 become non-conductive. As a result, the potential of the connection point between the drain electrode of the P-channel type MOS transistor 28 and the drain electrode of the N-channel type MOS transistor 26 rise to the boosted potential Vpp of the boosted potential node 2. The boosted potential Vpp at this time is Vcc of the precharge potential.
Accordingly, the N-channel transistor 29 becomes conductive and the P-channel transistor 30 becomes non-conductive. The potential of the second node 6 drops to the ground potential. Further, the P-channel type MOS transistor 22 becomes conductive since its source potential becomes 2Vcc, its gate potential becomes the ground potential and its drain potential becomes Vcc. Hence, the charges at the first capacitive element 8 flow into the boosted potential node 2 through the P-channel MOS transistor 22, thereby being stored at the load capacitor 3, so that the potential of the boosted potential node 2 is boosted to Vcc+.alpha.. The boosted portion .alpha. is determined by the capacitance shared between the capacitances of the first capacitive element 8 and the load capacitor 3.
When the clock signal drops to the ground potential at time T1, the potential of the first buffer means 7 also goes down to the ground potential, so that the potential of the first nodes 5 goes down to Vcc of the precharge potential by capacitive coupling of the first capacitive elements 8. Meanwhile, when the input of the level conversion circuit 23 changes to the ground level, the output node thereof changes to the boosted potential Vpp, which is outputted to the second node 6.
In the level conversion circuit 23 shown in FIG. 14, the N-channel type transistor 24 and the P-channel type transistor 28 become non-conductive, and the N-channel type transistor 26 and the P-channel type transistor 27 become conductive. Hence, the potential of the connection point between the drain electrodes of the P-channel type MOS transistor 28 and the N-channel type MOS transistor 26 drops to the ground potential. Further, the N-channel type transistor 29 becomes non-conductive, and the P-channel type transistor 30 becomes conductive.
The potential of the second node 6 is raised to the boosted potential Vpp of the boosted potential node 2. At this time, the boosted potential Vpp of the boosted potential node 2 is Vcc+.alpha.. Hence, the P-channel type MOS transistor 22 becomes non-conductive because its source potential is Vcc, its gate potential is Vpp, and its drain potential is Vcc+.alpha.. No charges flow from the boosted potential node 2 to the first node 5.
Next, when the clock signal is raised again to the power supply potential Vcc at time T2, the output of the first buffer means 7 is also raised from the ground potential to the power supply potential Vcc. The potential of the first capacitive element 8 is also raised in the same manner to above, thereby boosting the potential of the first node 5 up to two times Vcc, and the output of the level conversion circuit 23 goes down from the boosted potential Vpp to the ground potential. As a result, the P-channel type MOS transistor 22 becomes conductive, and the charges at the first capacitive element 8 flow into the boosted potential node 2 through the P-channel type MOS transistor 22, thereby further boosting the potential of the boosted potential node 2.
The potential of the boosted potential node 2 is boosted stepwise at every rise of the clock signal from the ground potential to the power supply potential Vcc. Finally, the boosted potential Vpp of 2Vcc is obtained at the boosted potential node 2. Hence, with the boosted potential generating circuit of FIG. 13, the output of the level conversion circuit 23 is a signal having a Vpp amplitude based on the boosted potential Vpp (which finally reaches 2Vcc) fed from the boosted potential node 2 and based on the clock signal of Vcc amplitude. However, large amount of the power is consumed by the boosted potential generating circuit of FIG. 13.
As described above, with the conventional boosted potential generating circuit of FIG. 6, the boosted potential Vpp obtained at the boosted potential Vpp is lowered by the threshold voltage Vth4 of the drive transistor, e.g., N-channel type MOS transistor 4, when the precharge potential is Vcc. If the precharge potential is lowered by a portion of the threshold voltage, the boosted potential Vpp is further lowered such that the boosted potential generating circuit cannot provide an adequate boosted potential.
With the boosted potential generating circuit of FIG. 10, the boosted potential Vpp obtained at the boosted potential node 2 is a potential equal to two times Vcc decreased by a portion the PN junction potential Vjv of the N-channel type MOS transistor 4. The boosted potential generating circuit must be produced with the triple well structure to achieve a boosted potential Vpp, but the number of process steps increases and the production costs become high.
Moreover, with the boosted potential generating circuit of FIG. 13, the boosted potential Vpp obtained at the boosted potential node 2 becomes a level of two times Vcc (power supply potential). However, the boosted potential generating circuit has large power consumption, since the amplitude level at the gate electrode of the P-channel type MOS transistor 22 is from the ground potential to the boosted potential Vpp.